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74VHC4066 Quad Analog Switch
April 1994 Revised February 2005
74VHC4066 Quad Analog Switch
General Description
These devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These switches have low "on" resistance and low "off" leakages. They are bidirectional switches, thus any analog input may be used as an output and visa-versa. Also the 4066 switches contain linearization circuitry which lowers the "on" resistance and increases switch linearity. The 4066 devices allow control of up to 12V (peak) analog signals with digital control signals of the same range. Each switch has its own control input which disables each switch when low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to VCC and ground.
Features
s Typical switch enable time: 15 ns s Wide analog input voltage range: 0-12V s Low "on" resistance: 30 typ. ('4066) s Low quiescent current: 80 PA maximum (74VHC) s Matched switch characteristics s Individual switch controls s Pin and function compatible with the 74HC4066
Ordering Code:
Order Number 74VHC4066M 74VHC4066MX_NL (Note 1) 74VHC4066MTC 74VHC4066MTCX_NL (Note 1) 74VHC4066N Package Number M14A M14A MTC14 MTC14 N14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Description
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Note 1: "_NL" indicates Pb-Free package (per JEDEC S-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Schematic Diagram
Top View
Truth Table
Input CTL L H Switch I/O-O/I "OFF" "ON"
(c) 2005 Fairchild Semiconductor Corporation
DS011677
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74VHC4066
Absolute Maximum Ratings(Note 2)
(Note 3) Supply Voltage (VCC) DC Control Input Voltage (VIN) DC Switch I/O Voltage (VIO) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 4) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times VCC VCC VCC 2.0V 4.5V 9.0V (tr, tf) 1000 500 400 ns ns ns 2 0 Max 12 VCC Units V V
0.5 to 15V 1.5 to VCC 1.5V VEE 0.5 to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC
600 mW 500 mW
40
85
qC
Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating -- plastic "N" package: 12 mW/qC from 65qC to 85qC.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage
(Note 5)
Conditions VCC 2.0V 4.5V 9.0V 12.0V TA 25qC Typ 1.5 3.15 6.3 8.4 0.5 1.35 2.7 3.6 100 50 30 120 50 35 20 10 5 5 170 85 70 180 80 60 40 15 10 10 TA 40 to 85qC Guaranteed Limits 1.5 3.15 5.3 8.4 0.5 1.35 2.7 3.6 200 105 85 215 100 75 60 20 15 15 Units V V V V V V V V
VIL
Maximum LOW Level Input Voltage
2.0V 4.5V 9.0V 12.0V
RON
Maximum "ON" Resistance See (Note 6)
VCTL VIS
VIH, IS
2.0 mA
4.5V 9.0V 12.0V 2.0V
: : : : : : : : : : PA
nA nA nA nA nA nA
V CC to GND
(Figure 1) VCTL VIS RON Maximum "ON" Resistance Matching IIN IIZ Maximum Control Input Current Maximum Switch "OFF" Leakage Current IIZ Maximum Switch "ON" Leakage Current ICC Maximum Quiescent Supply Current VCTL VIS VIN VCC VOS VIS VCTL VIS VCTL VOS VIN IOUT VIH, IS 2.0 mA
4.5V 9.0V 12.0V 4.5V 9.0V 12.0V
V CC or GND VIH V CC to GND VCC or GND 2 6V V CC or GND GND or VCC VIL (Figure 2) V CC to GND VIH OPEN (Figure 3) VCC or GND 0 PA
(Figure 1)
r0.05
6.0V 9.0V 12.0V 6.0V 9.0V 12.0V 6.0V 9.0V 12.0V 10 15 20 10 15 20
r0.5 r600 r800 r1000 r150 r200 r300
10 20 40
r60 r80 r100 r40 r50 r60
1.0 2.0 4.0
PA PA PA
Note 5: For a power supply of 5V r 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs for CMOS at the higher voltage and so the 5.5V values should be used. Note 6: At supply voltages (VCC - GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages.
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74VHC4066
AC Electrical Characteristics
VCC
2.0V6.0V VEE
0V12V, CL 50 pF (unless otherwise specified)
Conditions VCC 3.3V 4.5V 9.0V 12.0V TA 25qC Typ 25 5 4 3 30 12 6 5 60 25 20 15 40 100 30 10 8 7 58 20 12 10 100 36 32 30 TA 40 to 85qC Guaranteed Limits 20 13 10 11 73 25 15 13 125 45 40 38 MHz MHz ns ns ns ns ns ns ns ns ns ns ns Units
Symbol tPHL, tPLH
Parameter Maximum Propagation Delay Switch In to Out
tPZL, tPZH
Maximum Switch Turn "ON" Delay
RL
1 k:
3.3V 4.5V 9.0V 12.0V
tPHZ, tPLZ
Maximum Switch Turn "OFF" Delay
RL
1 k:
3.3V 4.5V 9.0V 12.0V
Minimum Frequency Response (Figure 7) 20 log (VO/VI)
RL VIS RL
600: 2 VPP at (VCC/2) 600:, F 1 MHz
4.5V 9.0V
3 dB
(Note 7)(Note 8) (Note 8)(Note 9) RL CL RL 600:, F 50 pF 600:, F 1 MHz 4.5V 9.0V RL F VIS VIS 10 k:, CL 1 kHz 4 VPP 8 VPP 4.5V 9.0V .013 .008 5 20 VCTL GND 0.5 15 10 10 % % pF pF pF pF 50 pF, 1 MHz 4.5V 9.0V 4.5V 9.0V
Crosstalk Between any Two Switches (Figure 8) Peak Control to Switch Feedthrough Noise (Figure 9) Switch OFF Signal Feedthrough Isolation (Figure 10) THD Total Harmonic Distortion (Figure 11) CIN CIN CIN CPD Maximum Control Input Capacitance Maximum Switch Input Capacitance Maximum Feedthrough Capacitance Power Dissipation Capacitance
Note 7: Adjust 0 dBm for F
52 50
100 250
dB dB mV mV
V(CT) VIL (Note 8)(Note 9)
42 44
dB dB
1 kHz (Null RL/RON Attenuation).
Note 8: VIS is centered at VCC/2. Note 9: Adjust input for 0 dBm.
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74VHC4066
AC Test Circuits and Switching Time Waveforms
FIGURE 1. "ON" Resistance
FIGURE 2. "OFF" Channel Leakage Current
FIGURE 3. "ON" Channel Leakage Current
FIGURE 4. t PHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output www.fairchildsemi.com 4
74VHC4066
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 7. Frequency Response
Crosstalk and Distortion Test Circuits
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk Between Any Two Switches
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74VHC4066
Crosstalk and Distortion Test Circuits
(Continued)
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
Typical Performance Characteristics
Typical "ON" Resistance Typical Crosstalk Between Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not exceed 0.6V (calculated from the ON Resistance).
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74VHC4066
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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74VHC4066
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74VHC4066 Quad Analog Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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